(1) Field of the Invention
The present invention relates to semiconductor manufacturing and is more particularly directed to expeditious conversion of embedded flash/EEPROM (electrically erasable programmable read only memory) products into other novel memory products.
(2) Description of the Related Art
In the manufacture of ROM products, it is usually the practice in the present manufacturing line to stock partially completed memory parts in a wafer bank and then finish them after having received a customer ordered ROM code, as will be explained more later. Then the completed wafer is assembled and tested before the product is shipped to the customer. Important factors in running a memory manufacturing line include turn-around-time (TAT), time to market and cost that are associated with the making of the product.
Digital memories allow for data storage (or writing) as well as data retrieval (or reading). Memories in which both of these functions can be rapidly and easily performed, and whose cells can be accessed in random order, are referred to as random-access memories (RAMs). Read-only memories (ROMs) are those in which only the read operation can be performed rapidly. As is known, entering data into a ROM, however, is referred to as programming the ROM, to emphasize that this operation is much slower than the writing operation used in RAMs.
In semiconductor RAMs, information is stored on each cell either through the charging of a capacitor or the setting of the state of a bistable flip-flop circuit. With either method, the information on the cell is destroyed if the power is interrupted. Such memories are therefore referred to as volatile memories. When charge on a capacitor is used to store data in a semiconductor-RAM cell, the charge needs to be periodically refreshed, since leakage currents will remove it in a few milliseconds. Hence, volatile memories based on this storage mechanism are known as dynamic RAMs, or DRAMs.
If the data is stored (i.e., written into the memory) by setting the state of a flip-flop, it will be retained as long as power is connected to the cell (and no other write signals are received). As is known in the art, RAMs fabricated with such cells are called static RAMs, or SRAMS.
It is often desirable to use memory devices that will retain information even when the power is temporarily interrupted (or when the device is left without applied power for indefinite periods). Magnetic media offer such nonvolatile-memory storage In addition, a variety of semiconductor memories have been developed with this characteristic. At present, virtually all such nonvolatile memories are ROMs. While data can be entered into these memories, the programming procedure varies from one type of ROM to the other.
The first group of nonvolatile memories consists of those ROMs in which data is entered during manufacturing, and cannot subsequently be altered by the user. These devices are known as masked ROMs (or simply ROMs). The next category consists of memories whose data can be entered by the user (user-programmable ROMs). In the first example of this type, known as a programmable ROM, or PROM, data can be entered into the device only once.
In the remaining ROM types, data can be erased as well as entered. In one class of erasable ROMs, the cells must be exposed to a strong ultraviolet light in order for stored data to be erased. These ROMs are called erasable-programmable ROMs, or EPROMs. In the final type, data can be electrically erased as well as entered into the device; these are well-known as EEPROMs. The time needed to enter data into both EPROMs and EEPROMs is much longer than the time required for the write operation in a RAM.
The most cost effective, high volume production non-volatile memory used principally for program or instruction storage is the mask programmable Read Only Memory (ROM). The mask programmable ROM is dense, offers high access speed, and requires no special processing steps when used in standard MOS logic processes. However, while in development stages of the ROM code for these products, they often need to be re-programmed, which requires generation of a mask and the processing of at least a few wafers for code verification. The re-programming can be quite costly. Furthermore, the poor TAT can result in high chip development cost and costly xe2x80x9ctime to marketxe2x80x9d delays. Given the program complexity of today""s micro-controllers and DSPs, repeated changes to program code or software is common.
One solution that has been found in prior art is the use of emulator chips. These chips remove the ROM and port the ROM addresses, control, and data I/O to chip pins for interface to an external Programmable Read Only Memory or PROM. Another method that may be used for code development is based on fuse or anti-fuse technology. Because of a reduced current requirement for programming the cell, anti-fuse technology has been preferred over fuse technology for MOS based memories. Anti-fuse technology uses an insulating element in the contact of an addressable cell which can be shorted by passing a relatively high voltage and current through the insulating element thereby causing a rupture or short and thus, a state change from an insulating element to a conductive element. Insulators include oxide (SiO2), silicon nitride (Si3N4), various combinations of oxides and nitrides, polysilicon, and amorphous silicon. These types of memories are used in permanent applications requiring reliability and, therefore, need special high voltage transistors to program the cells. The addition of these special transistors to the process adds to its cost and are not required.
Worley, in U.S. Pat. No. 6,021,079 discloses an anti-fuse PROM which is embedded into a conventional CMOS process with some additional process steps and additional area for the wire circuitry. Nominal, low voltage transistors are used to program the PROM such that these transistors remain functional some time after programming for the purposes of verifying functionality of the memory""s programming code. Once the program code has been verified a low cost production version of the part then can be made using standard ROM mask programming.
Another known programming method is called oxide programming which provides for two types of metal oxide semiconductor field effect transistors (MOSFET) by the use of different gate oxide layer thickness for each transistor type. Each oxide layer thickness corresponds to a different transistor threshold voltage. In programmed cells, the thickness of the gate oxide layer is about the same thickness as the field oxide, thereby providing a transistor which is permanently xe2x80x9coffxe2x80x9d or in a logic xe2x80x9c0xe2x80x9d state. Unprogrammed cells include typical thicknesses for the gate oxide layer so that the transistor is xe2x80x9conxe2x80x9d or in logic xe2x80x9c1xe2x80x9d state. A disadvantage of the field oxide programming method includes a longer product TAT as measured from the programming step. Much of the process occurs after programming the gate oxide layers of the cells. Huang, et al., in U.S. Pat. No. 6,037,222 disclosed such a method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology.
On the other hand, You, et al., in U.S. Pat. No. 6,020,241 teach a threshold voltage implant method of manufacturing a ROM that is code implanted late in the process after the first level metal, thus reducing the TAT to ship a customer order. This method changes the transistor threshold voltage by ion implanting the transistor gates for programmed cells. In n-channel devices, impurities such as boron are implanted into exposed gates which raise their threshold voltage. The implant forces the gates of the cells permanently to an xe2x80x9coffxe2x80x9d state. Unexposed gates are not implanted and therefore provide cells at an xe2x80x9conxe2x80x9d state. Heavy implants, however, often create damage to the thin gate oxide region. Damage to the gate oxide region causes higher parasitic junction capacitance between the source (or drain) and channel region of the metal oxide semiconductor field effect (MOS) transistor. Higher parasitic junction capacitance leads to an increase in average word-line capacitance, and often results in slower speeds.
It is often desirable to apply the ROM code onto the partially completed devices during a latter part of the manufacturing process. By applying the code at the later process, it takes less time to process the wafer from that point to completion. Less time for completion corresponds to a faster product turn-around-time. As the life cycle of integrated circuits become shorter, it is more desirable to fabricate products with shorter turn-around-times.
Industry relies on two general types of ROM array structures and combinations thereof using cells fabricated by the described methods. Such array structures include the serial ROM cell structure which is a NAND gate type structure and the parallel ROM cell structure known as the NOR gate type structure. Characteristics of NOR and NAND gate type structures are often competing.
A parallel NOR gate type structure includes a set of MOS transistors connected in parallel to the bit-line. The parallel structure typically increases the speed of the ROM but decreases bit or cell packing density. The lower density is caused by the use of a larger cell size. The larger cell size exists froth the contacts needed for each cell.
Alternatively, a serial NAND gate type structure often increases cell packing density or bit density but provides a slower operation speed. The serial structure forms a denser structure since no contact holes are required. Higher memory requirements for state-of-art devices use the denser serial NAND gate type structure.
FIG. 1 is a cross-sectional view of a programmed cell for a typical prior art ROM device fabricated by the threshold voltage implant method. The programmed cell may be used for a NAND gate type array structure. The threshold voltage implant method changes an enhancement mode n-channel metal oxide semiconductor field effect transistor (MOSFET) into a depletion mode device by implanting n-type ions into the channel region of the MOS transistor. The n-type implant programs or codes the transistor of the cell. In the present invention, however, p-type code is used for an enhancement mode n-channel MOS for the ROM process that is disclosed later in the embodiments of the invention.
The programmed cell shown in FIG. 1 includes a depletion mode MOS transistor in a semiconductor substrate (10). The programmed cell defines a p-type well region (20), field oxide regions (13), gate oxide region (30), and source/drain regions (15), (17). The programmed cell also defines an implanted channel region (19) under the gate oxide region (30). The implanted channel region changes the enhancement mode MOS transistor into the depletion mode transistor. A polysilicon gate (40), gate sidewall spacers (55), borophosphosilicate glass layer (50) (BPSG), metallization layer (60), and surface passivation (70) are also shown. The polysilicon gate, source region, drain region, and channel region define the depletion mode MOSFET.
Each cell, such as the cell of FIG. 1, corresponds to a region for storing bits of information in a ROM semiconductor integrated circuit chip. Thousands and even millions of these microscopically small regions make up a core memory area (or active cell area) of the ROM chip. The completed ROM chip also includes peripheral circuits, interconnects, and bonding pad.
A ROM embedded SRAM utilizing an existing support circuitry of the SRAM array is disclosed by Marr in U.S. Pat. No. 6,041,008. By disabling or not disabling SRAM cells by removing or not removing the ground or power connections to each cell in different combinations, a pair of SRAM cells are used to permanently store a specified logic state, i.e., functions as a ROM cell. A self-aligned source/drain mask ROM memory cell using trench etched channel is shown in U.S. Pat. No. 5,751,040 by Chen, et al. And an apparatus for repairing faulty program segments in embedded microprocessor systems is disclosed by Hsu in U.S. Pat. No. 5,938,774.
What is also needed in the art is a method for the customers not to re-design their ROM parts so that they can switch their Flash/EEPROM products to ROM parts easily and with the same layout. Such a method is disclosed later in the embodiments of the present invention.
It is therefore an object of the present invention to provide a method of using embedded flash/EEPROM as a prototype and use the same database to form embedded ROM products in order to improve turn-around-time in the manufacturing line, time-to-market, and reduce cost for the customer.
It is another object of the present invention to provide a method for making this switching process from embedded flash/EEPROM to embedded ROM possible without any re-design effort on the part of the customer.
It is still another object of the present invention to provide a method of removing certain masking steps and switching the manufacturing process from embedded flash/EEPROM to pure logic or mixed mode process with a ROM code.
It is yet another object of the present invention to provide a method of combining the manufacture of embedded flash/EEPROM and embedded ROM products into the same manufacturing line by a judicious skipping of certain process steps and modifying a few masks in the former, and implanting a ROM code into the latter.
It is also yet another object of the present invention to provide a method of doing business directed to the manufacture of embedded ROM products with simple design changes and without much time and effort on the part of the customer.
These objects are accomplished by the converting of an embedded Flash/or EEPROM process to a logic process with the same design. Different Flash/EEPROM cell structures, including split-gate flash and stacked gate flash, can have the same approach. With split-gate flash as an example, these objects are accomplished by providing an embedded flash/EEPROM prototype substrate having different well regions; defining a cell region and a periphery region further comprising a low-voltage LV-region, and a high-voltage HV-region in said substrate; forming a gate oxide layer on said substrate including over said cell region and said periphery region; depositing a first polysilicon layer over said gate oxide layer on said substrate; forming a nitride layer over said first polysilicon layer; patterning said nitride layer to form openings to expose portions of said polysilicon layer; oxidizing said portions of said first polysilicon layer to form poly-oxide as caps over said polysilicon layer; removing said nitride layer to expose other portions of said first polysilicon layer not protected by said caps; removing said other portions of said first polysilicon layer by using said poly-oxide as a hard-mask to form floating gate underlying said cap; forming a first thick interpoly oxide over said substrate, including over said cell region and over said periphery region; removing said first thick interpoly oxide (IPO) over said periphery LV-region using one photo-mask; forming a second interpoly low-voltage LV-oxide over said cell region and over said periphery region; forming a second polysilicon layer over said LV-oxide and said thick interpoly oxide over said substrate, including said cell region and said periphery region; patterning said second polysilicon layer to form a control gate over said cell region and a poly gate over said periphery region; performing a lightly doped drain (LDD) implant over said substrate; forming oxide/SiN spacers along every exposed polysilicon edge, including sides of said floating gate, control gate and gate poly; performing source/drain implant; forming an interlevel dielectric layer (ILD) over said substrate; planarizing said ILD layer using either etch-back or CMP methods; forming a contact hole in said ILD layer; forming metal in said contact hole and continuing to finish said embedded flash/EEPROM memory prototype; performing programming simulation for a ROM product using said embedded flash/EEPROM prototype; generating data to form ROM code for said ROM, product; providing a ROM product substrate having a cell region and a periphery region; forming a ROM gate oxide, comprising LV-gate oxide, over said ROM product substrate, including said cell region and said periphery region; forming a gate polysilicon layer over said ROM gate oxide layer; patterning said gate polysilicon layer to form a polysilicon gate; performing an LDD implant over said ROM substrate; forming oxide/SiN spacers along sides of said polysilicon gate; performing source/drain implant over said ROM substrate; forming a ROM mask; performing ROM code implant, using said ROM code; forming an ILD layer over said substrate; forming a contact hole in said ILD layer; and forming metal in said contact hole to and continuing to complete the said flash ROM product.
The method of doing business objects are accomplished by providing a first manufacturing process for an embedded Flash or embedded EEPROM product; manufacturing said embedded Flash or embedded EEPROM product by said first manufacturing process for customer""s prototyping activities with more flexibility that customers can shorten time to market; providing a second manufacturing process for an embedded ROM product that is similar to the first manufacturing process; manufacturing said embedded ROM product by said second manufacturing process, whereby said customer has to do minimal re-design in converting a design of said embedded Flash or embedded EEPROM product to a design of said embedded ROM product.